The present invention relates to circuit testing, and more particularly, to die fault testing utilizing Exclusive-OR gates.
Not all die (chips) on a wafer operate as intended. Some may have internal nodes that are stuck at a logical 1 or 0. Consequently, it is desirable for a functional test on a die to cover as many internal circuit nodes as practical. In a functional test, a tester drives input vectors on the input pads of the die, and compares the output vectors on the output pads to the output vectors generated by a simulation running the same functional test on a model of the die. This model may be, for example, a behavioral model, a RTL (Register Transfer Language) model, a gate-level model, or a transistor (circuit-level) model. For an internal node to be tested, the input vector should toggle the node (change its logic state), and the toggling of the node should cause an observable change in the output vector. Thus, there should be good controllability (node toggling), and good observability.
It is found that for many die, it may at times be difficult to obtain a fault coverage of 90% or more, even though a toggle coverage test may show a toggle coverage of 99%. In such cases, there may be many nodes that are easily toggled (good controllability), but such that the toggling is not easily observed in the output vectors (poor observability). If the tester is able to sample internal nodes directly and to utilize longer test vectors, then it is easier to obtain a high fault coverage for functional tests. However, this is not practical because most of the internal nodes in a die are not directly controlled or observed, and because the test has a limited number of vectors that may be examined. Consequently, there is a need for improved practical methods of testing.